Chip-Multiprocessor using Data Driven Multithreading (DDM) and Conventional Microprocessors Cores

Seminar | 905 (Auditório Omega) | 14:00

Pedro Trancoso,

Department of Computer Science, University of Cyprus


Data-Driven Multithreading (DDM) is a non-blocking multithreading execution model that tolerates inter-node latency by scheduling threads for execution based on data availability. In order to exploit the benefits of dataflow execution without the penalties of custom designed systems, we show how DDM may be implemented in systems equipped with regular off-the-shelf microprocessors. In addition, we use the characteristics of DDM scheduling to implement a cache management policy (CacheFlow) that further improves the performance.

In this presentation we show a brief evaluation of DDM and CacheFlow by simulating the execution of several SPLASH-2 scientific applications on a DDM network of workstations (D2NOW) with up to 32 nodes. The results are very encouraging as the speedup observed for a 16- and 32-node configuration was 14.4 and 26.0, respectively. In addition, we show how this work will be extended to the Chip-Multiprocessor architecture, as well as preliminary results for this new implementation.


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