The objectives of the ESDA group include all aspects of Research and Development of Electronic Systems, and Research and Development of Tools and Algorithms for Design Automation. Current emphasis is given to the area of Reconfigurable Systems.
The research on Reconfigurable Computing gives emphasis both to the development of new dedicated (co)synthesis algorithms able to automatically accelerate generic applications by migrating its more computational intensive parts to dynamically configurable hardware, to the development of generic reconfigware (reconfigurable hardware) components to be re-used in generic applications and to the design of dedicated reconfigurable computing systems for specific application examples.
We are developing an automated synthesis framework, dedicated to the acceleration of generic algorithmic applications to reconfigurable computing systems. The main results already achieved in this research involve the development of a hardware compiler that accepts programs previously compiled to JavaÔ bytecodes. The new algorithms combine state-of-the-art techniques from the compiler and design automation worlds to achieve the required performance improvements. In particular, new techniques for architecture and performance driven compilation of software programs into reconfigurable hardware have been developed.
This research has been complemented at the system-level by the development of new co-synthesis techniques to implement data-intensive applications using heterogeneous hardware/software architectures with dynamically reconfigurable hardware/software components.
Emphasis is now also being given to the design of dedicated reconfigurable systems for applications that cannot be adequately handled by pure software systems due to its large computational requirements. Reconfigurable hardware algorithms able to efficiently exploit the inherent parallelism in many of these problems are under study. Because of the possibility of online reconfiguration, these algorithms can be instance specific and make use of virtualization if the circuit is too large to fit the platform. In particular we have been studying algorithms for the reconfigware acceleration of genetic algorithms and neural networks.