Cyber-physical MPSoC Systems: Future Multi-Core Architectures for reliable Mobility & Technologies
Prof. Dr.-Ing. Juergen Becker,
Karlsruhe Institute of Technology – KIT. Dept. Electrical Engineering & Information Technology. Institute for Information Processing – ITIV. Karlsruhe, Germany. –
The field of embedded electronic systems, nowadays also called cyber-physical systems, is still emerging. A cyber-physical system (CPS) is a system featuring a tight combination of, and coordination between, the system’s computational and physical elements. Today, a pre-cursor generation of cyber-physical systems can be found in areas as diverse as aerospace, automotive, chemical processes, civil infrastructure, energy, healthcare, manufacturing, transportation, entertainment, and consumer appliances. This generation is often referred to as embedded systems. In embedded systems the emphasis tends to be more on the computational elements, and less on an intense link between the computational and physical elements.
Multipurpose adaptivity and reliability features are playing more and more of a central role, especially while scaling silicon technologies down according to Moore’s benchmarks. Leading processor and mainframe companies are gaining more awareness of reconfigurable computing technologies due to increasing energy and cost constraints. My view is of an “all-win-symbiosis” of future silicon-based processor technologies and reconfigurable circuits/architectures. Dynamic and partial reconfiguration has progressed from academic labs to industry research and development groups, providing high adaptivity for a range of applications and situations. Reliability, failure-redundancy and run-time adaptivity using real-time hardware reconfiguration are important aspects for current and future embedded systems, e.g. for smart mobility in automotive, avionics, railway, etc.. Thus, scalability, as we have experienced for the last 35 years is at its end as we enter new phases of technology and certification within safety-critical application domains. Beyond the capabilities of traditional reconfigurable fabrics (like FPGAs), the so-called Multi-/Many-Core solutions are confirmed on the future semiconductor roadmaps. This requires new solutions for programming and integrating such kind of parallel and heterogeneous architectures and platforms, e.g. especially in safety-critical application domains like automotive, avionics and railway.
In addition: Nano Era with corresponding circuits/architectures allow for micro-mechanical switches that enable new memory and reconfiguration technologies with the advantage of online chip adaptivity and non-volatility. Transient faults may lead to unreliable information processing as information in nanosized devices is much less. Power consumption and related problems present a challenge where information is processed within a smaller area/volume budget. This includes the consideration of appropriate fault tolerance techniques and especially the discussion of necessary efficient and online self-repairing mechanisms for driving such kind of future silicon and non-silicon based technologies and architectures.
This keynote will finally discuss in detail the corresponding challenges and specifically outline the promising perspectives for future multi-/many-core as well as dynamically reconfigurable, complex, adaptive and reliable systems-on-chip, for embedded and also general purpose computing systems.
Juergen Becker is Full Professor for Embedded Electronic Systems in the department of Electrical Engineering and Information Technology at Universitat Karlsruhe (TH). His actual research is focused on industrial-driven System-on-Chip (SoC) integration with emphasis on adaptivity, e.g. dynamically re-configurable hardware architecture development and application in automotive and communication systems. Prof. Becker is Head of the Institute for Information Processing (ITIV) and Department Director of Electronic Systems and Microsystems (ESM) at the Computer Science Research Center (FZI). From 2001- 2005 he has been Co-Director of the International Department at Universitat Karlsruhe (TH), and from 2002-2008 Associate Editor of the IEEE Transactions on Computers. He is author and co-author of more than 300 scientific papers, and active as general and technical program chair- man of national / international conferences and workshops. He is executive board member of the ger- man IEEE section, Board member of the GI/ITG Technical Committee of Architectures for VLSI Circuits, and Senior Member of the IEEE. Since October 2005 Prof. Becker has been Board Member and Vice-President (“Prorektor”) for Studies and Teaching at Universitat Karlsruhe (TH), and from October 2009 – April 2012 Chief Higher Education Officer (CHEO) in the new Karlsruhe Institute of Technology – KIT – the unique merger of a large national research lab in the Helmholtz Society as well as of a prominent state university of Baden-Wuerttemberg in Germany. Since July 2012 Prof. Becker is Secretary General of CLUSTER – the association of 12 leading European technical universities.
Luis Miguel Teixeira D Avila Pinto da Silveira
Anfiteatro do Complexo Interdisciplinar, IST Alameda
Mathematics, Physics & Machine Learning Seminar Series (Online)
The Mathematics, Physics & Machine Learning seminar series has started on October 2020 and runs until March 2021.
The seminars aim to bring together mathematicians and physicists interested in machine learning (ML) with ML and AI experts interested in mathematics and physics, with the goal of introducing innovative Mathematics and Physics-inspired techniques in Machine Learning and, reciprocally, applying Machine Learning to problems in Mathematics and Physics.
Attendance is free but registration is required.
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International European Conference on Parallel and Distributed Computing
The 27th International European Conference on Parallel and Distributed Computing (Euro-Par 2021) will take from August 30 to September 3 2021 in Lisbon.
Euro-Par is the prime European conference covering all aspects of parallel and distributed processing, ranging from theory to practice, from small to the largest parallel and distributed systems and infrastructures, from fundamental computational problems to full-fledged applications, from architecture, compiler, language and interface design and implementation, to tools, support infrastructures, and application performance aspects.
The 2021 edition of Euro-Par will be organized as a collaboration between INESC-ID and Instituto Superior Técnico (IST).
– Abstract Submission: February 5, 2021
– Paper Submission Deadline: February 12, 2021
– Author Notification: April 30, 2021
– Camera-Ready Papers: June 6, 2021
More information is available here.