Dr. Raóul Velazco,

Lab, Intitut National Polytechnique de Grenoble


Microelectronic circuits operating in radiation environments can be affected by the so-called Single Event Upsets (S.E.U.) phenomenon. SEUs, also referred as “upsets”, “soft errors” or “bit flips”, are mainly responsible for transient (non destructive) changes in the information stored in memory cells within integrated circuits. The cause of SEUs is the creation of a spurious current pulse in sensitive areas of the circuit. This current pulse appears as the consequence of the ionization produced from the interaction of energetic particles with the silicon substrate.

Since the last 20 years SEUs have been a major concern for space applications due to the presence of charged particles (heavy ions, protons) in space environment. The constant improvements accomplished by the microelectronics manufacturing technology, make the today’s integrated circuits operating in the Earth’s atmosphere potentially sensitive to SEUs. Indeed, upsets observed in aircraft’s equipment and even in systems operating at ground level, have been explained by the interaction of neutrons present in the atmosphere. Notice that in this case, the incident particle has no charge, but the ionization is provoked by the daughter particles resulting from the intereaction between the neutron and atoms present in the silicon substrate.

Perturbations provoked by Single Event Upsets (SEUs) increase with the reduction of transistor\\\’s features. In this talk it will be presented a strategy allowing estimating SEU error-rates based on a limited radiation ground testing (performed in particle accelerators) and fault injection results. A flexible and versatile test platform, well suited to implement such a strategy will be described. Experimental results obtained for different processors will illustrate the accuracy of error rate predictions resulting from the use of the proposed error-rate prediction strategy.


Date: 2006-May-05     Time: 11:00:00     Room: 336

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