Anton Chichkov,



Cost-effective test of semiconductor products in DSM (Deep Sub-Micron) technologies is a challenging problem. High-quality test, leading to extremely low defect levels, or escape rates (in the order of few ppm (parts per million)) requires a unified approach of intelligent management of different test strategies. Digital test is difficult, analog and mixed-signal design and test is even more demanding. The author works in worldwide leading company and will address, from an industrial point of view, the following topics:
Need for test
Cost of test and DFT (Design for Testability)
Link yield coverage and PPMs
Challenges for 0 PPM strategies
Some real cases of RMA
Some possible directions to go with DFT
Addressing Bridging Faults
Addressing Open Faults
Analogue BIST
Overview of state of the art in the industry for test development and coverage


Date: 2006-Jun-01     Time: 11:00:00     Room: IST, Torre Norte, Anfiteatro EA4

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