Solving SAT with an Embedded Processor and Reconfigurable Logic in an FPGA
Carlos Jorge Chumbinho Tavares
José T. de Sousa,
Inesc-ID –
Abstract:
In this talk a SAT solver implemented in an FPGA and using a soft processor (MicroBlaze) will be described
Date: 2004-Nov-18 Time: 11:00:00 Room: 336
For more information:
- sca.inesc-id.pt/~jts
- jts@inesc-id.pt
- 213100215
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