Solving SAT with an Embedded Processor and Reconfigurable Logic in an FPGA
Seminar
Carlos Jorge Chumbinho Tavares
José T. de Sousa,
Inesc-ID –
Abstract:
In this talk a SAT solver implemented in an FPGA and using a soft processor (MicroBlaze) will be described
Date: 2004-Nov-18 Time: 11:00:00 Room: 336
For more information:
- sca.inesc-id.pt/~jts
- jts@inesc-id.pt
- 213100215
Upcoming Events
15 February
16:00 - 17:00
INESC-ID ESR Talks – February 2023
If you are a masters/PhD student or a postdoctoral fellow, come and present your work in an informal and friendly environment – and savour some tasty snacks!
Individual talks will be 10-15 minutes plus time for feedback. Enroll on your selected date by emailing pedro.ferreira[at]inesc-id.pt.
Happening on the second Wednesday of every month (4pm-5pm):
- 15 February (Alves Redol, Room 9)
- 15 March (Alves Redol, Room 9)
- 12 April (Alves Redol, Room 9)
- 10 May (Alves Redol, Room 9)
- 14 June (Alves Redol, Room 9)
- 12 July (Alves Redol, Room 9)
We hope to see you there!
No event found!