Applications of Rewriting-Logic in Reconfigurable Hardware Design Space Exploration
University of Karlsruhe –
Reconﬁgurable architectures are increasingly being used for digital signal
processing applications. The typical development process for DSP applications
starts with a set of mathematical equations which are manipulated and
interpreted by the developer, and then manually translated into a lower
abstraction level. The developer must consider many different implementation
approaches and parameters in order to obtain the best trade-offs for the
given application on the target architecture.
The exploration of different approaches and implementation alternatives is
a very complex, time consuming and error-prone process which requires a lot
of expertise from the developer. To address this problem, a novel tool ﬂow
based on rewriting logic is being developed.
The talk presents the toolflow and some applications examples.
Date: 2006-Sep-27 Time: 16:00:00 Room: 336
For more information:
INESC-ID ESR Talks – February 2023
If you are a masters/PhD student or a postdoctoral fellow, come and present your work in an informal and friendly environment – and savour some tasty snacks!
Individual talks will be 10-15 minutes plus time for feedback. Enroll on your selected date by emailing pedro.ferreira[at]inesc-id.pt.
Happening on the second Wednesday of every month (4pm-5pm):
- 15 February (Alves Redol, Room 9)
- 15 March (Alves Redol, Room 9)
- 12 April (Alves Redol, Room 9)
- 10 May (Alves Redol, Room 9)
- 14 June (Alves Redol, Room 9)
- 12 July (Alves Redol, Room 9)
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