Abstract:

With IC technology steadily progressing into nanometer dimensions, precise control over all aspects of the fabrication process becomes an area of increasing concern. The impact of process parameter variations in circuit performance is becoming quite significant, particularly in what concerns timing. In this new context, traditional timing verification methodologies are starting to fail. Improving this situation requires tools that are better suited to handle realistic process variations and the complex inter-relations that exist between those variations. In this talk we propose a variation-aware methodology for timing analysis of ICs. We present new delay modeling techniques, where cell and interconnect delays are modeled by affine functions of the process parameters, rather than fixed numeric values. Additionally, we present a variation-aware timing analysis methodology that, using parametric delay models, extends traditional corner-based signoff techniques. Both contributions can be easily integrated into existing timing engines, producing insightful information for effectively guiding manual or automated circuit optimization in a variation-aware fashion.

Date: 2007-Mar-01     Time: 14:00:00     Room: 336

For more information:

• las@inesc-id.pt