Abstract:

The lecture will be organized in three parts. The first part will be devoted to the University of Niš, and Computers Science Department at the Faculty of Electronic Engineering. We will briefly explain the organizational structure of the University, commenting research and teaching activities at Computer Science Department.

A review of our research in the field of design and application of folded architectures will be given in the second part. We will present few design examples emphasizing specific design goals. As the main design example will present the synthesis of configurable bit-plane processing arrays for FIR filtering. The H.264/AVC application of configurable folded array, as the deblocking filter implementation with low-gate count, will be presented. Results of the architecture implementation as a real-time deblocking accelerator for mobile embedded computing platforms will be given.

The third part of presentation addresses our latest results in the error tolerant architecture design. We will present a method for trading computational correctness for an additional chip area involved by fault-tolerance implementation. The method will be described in a formal way and demonstrated for the BP array. A mathematical path based on transitive closure that generates an error significance map for the BP array will be explained. The design tradeoff will be demonstrated through FPGA implementation.

Date: 2008-Apr-10     Time: 11:00:00     Room: 336

For more information:

• pedro.tomas@inesc-id.pt