Frederico Pratas,

Inesc-ID –

Abstract:

Power consumption has become a very important metric and challenging research topic in the design of microprocessors in the recent years. This work improves power efficiency of superscalar processors through instruction reuse at the execution stage. A new method for reusing instructions that compose small loops is proposed: instructions are first buffered in the Reorder Buffer and reused afterwards without the need for dynamically unrolling the loop, as commonly implemented by the traditional instruction reusing techniques. In order to evaluate the proposed method we modified the sim-outorder tool from Simplescalar and the Wattch Power Performance simulators. Several different configurations and benchmarks have been used during the simulations. The obtained results show that by implementing this new method in a superscalar microarchitecture, the power efficiency can be improved without significantly affecting neither the performance nor the cost.

 

Date: 2008-Apr-29     Time: 11:00:00     Room: 336

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