Francesco Regazzoni,

University of Lugano


Side channel analysis is a technique for attacking cryptographic algorithm implementations that exploits information leaked while secret data is being processed.
In this talk, after an introduction to power analysis attacks, a design flow that enables to prove the robustness against power analysis attacks without the need of manufacturing and testing the chip will be presented. Contrary to past approaches on this subject, which have argued robustness qualitatively or have required hardware manufacturing to prove it, the robustness is evaluated with real attacks, on traces generated at SPICE level in a reasonable amount of time.
The talk will conclude with the presentation of two real examples where the proposed design and simulation flow was used: the exploration of MOS – Current Mode Logic as possible countermeasure and the evaluation the effects of fault attacks protections on DPA resistance.


Date: 2008-Jul-25     Time: 10:30:00     Room: 336

For more information: