Abstract:

Integrated circuits contain millions of electronic switches connected
by kilometers of interconnect, on an area of about 1 square cm. The
electrical behavior of such circuits strongly depends on the
capacitive, resistive and even inductive properties of the interconnect
network and the substrate. Since these parasitic properties can only be
approximately accounted for during design, it is necessary for
verification purposes to translate the layout (physical design) of an
integrated circuit back into an electrical netlist. This process is
called parasitics extraction. This presentation will first explain the
background and challenges of parasitics extraction, to be followed by a
review of some recent results for modeling of interconnects and
substrate. Specific topics include model order reduction and
manufacturing variability. The presentation will conclude with a brief
overview of open problems.

Nick van der Meijs (NL, 1959) received his PhD from
Delft University of Technology in 1992, where he currently is an
associate professor. His teaching responsibilities include circuit
theory, VLSI design, and electronic design automation. He is also
Director of Studies for the EE program. His research interests circle
around physical/electrical aspects of deep-submicron integrated
circuits, including ultra-deep-submicron design, modeling and
extraction of physical/electrical effects in large integrated circuits,
and efficient (practical) algorithms for electronic design automation
in general. He is leading a research group on Physical Modelling and
Verification of parasitic effects in integrated circuits and is a
principal developer of the SPACE layout to circuit extractor. He has
served on various program committees of international conferences, is
the chair of the IEEE Benelux Circuits and Systems chapter and previous
chair of the ProRISC micro-electronics workshop in the Netherlands. He
is a recipient of a personal ~0.9M Euros “pioneer” research grant in
the Netherlands. (http://ens.ewi.tudelft.nl/~nick/)

Date and local: Tuesday, September, 30 2008, 11h00, room 336 at INESC-ID, Lisbon.

Date: 2008-Sep-30     Time: 11:00:00     Room: 336

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