New architectures for the final scaling of the CMOS world
Luigi Carro,
Universidade Federal do Rio Grande do Sul –
Abstract:
As technology scaling reaches the physical limits of silicon,
several new problems must be addressed, from the design of
low-power but high performance circuits, to the reliability issue
of weak transistors and mixed technologies (nanowrires, SET, etc).
These technological problems will impact several layers of the
current abstraction stack that covers computers and software
production. New architectural solutions that explore parallelism
at different granularity must be sought, not only for
performance/energy trade-offs, but also as a means to assure
reliability, fault tolerance and yield, thanks to regularity. This
talk presents some ideas on this direction, covering future
processor architectures and quaternary logic circuits, discussing
technologies that can deal with this multivariable problem.
Luigi Carro was born in Porto Alegre, Brazil,
in 1962. He received the Electrical Engineering and the MSc
degrees from Universidade Federal do Rio Grande do Sul (UFRGS),
Brazil, in 1985 and 1989, respectively. From 1989 to 1991 he
worked at ST-Microelectronics, Agrate, Italy, in the R&D group. In
1996 he received the Dr. degree in the area of Computer Science
from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. He
is presently a professor at the Applied Informatics Department at
the Informatics Institute of UFRGS, in charge of Computer
Architecture and Organization disciplines at the undergraduate
levels. He is also a member of the Graduation Program in Computer
Science at UFRGS, where he is co-responsible for courses on
Embedded Systems, Digital signal Processing, and VLSI Design. His
primary research interests include embedded systems design,
validation, automation and test, fault tolerance for future
technologies and rapid system prototyping. He has published more
than 150 technical papers on those topics and is the author of the
book Digital systems Design and Prototyping (2001-in portuguese)
and co-author of Fault-Tolerance Techniques for SRAM-based FPGAs
(2006-Springer). For the latest news, please check
http://www.inf.ufrgs.br/~carro.
Seminar organized by the
ALGOS group
algos.inesc-id.pt.
Date: 2008-Oct-16 Time: 11:00:00 Room: 336
For more information:
- 213100399
Upcoming Events
INESC Brussels HUB Winter Meeting 2023

This edition of the HUB Winter Meeting will be co-organised with Science Business and will take place on the 30 and 31 January, in Lisbon, at Instituto Superior Técnico, Department of Computer Science and Engineering.
Please see below a summary of the agenda, this will be updated on the INESC Brussels HUB website regularly (confirmed speakers and other relevant info). Places for onsite participation are limited so registration is mandatory. Online participants will be sent a ZOOM link for each specific session on the 27th January.
INESC Brussels HUB website: https://hub.inesc.pt/
Monday, 30 January
a) Digital Europe Programme & Chips Act: state of play and possibilities for INESC.
9h to 10h30 GMT
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c) Networking Lunch (for all onsite participants).
d) Roundtable: From rhetoric to reality – Embedding international strategy in the DNA of research organisations.
(Closed-door, roundtable workshop, Chatham House rules, open to INESC researchers and administrators, external participants by invitation only).
e) Networking Dinner
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Tuesday, 31 January
f) Workshop: How they did it? Strategic positioning for structural success in Horizon Europe: a discussion of best practices.
(Exclusive for INESC researchers, administrators and international invited speakers).
g) The public consultation on European R&I Programmes: Towards FP10.
(Closed-door, roundtable workshop, Chatham House rules, open to INESC researchers and administrators, external participants by invitation only).
h) Networking Lunch (for all onsite participants).
i) Management Committee meeting (Directors and POB members)
The HUB Winter Meeting aims at bringing together researchers and administrators from the 5 INESC institutes, affiliated higher education institutions in Portugal and abroad, with key European and global players, to:
– Discuss key research and innovation issues at EU level.
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