New architectures for the final scaling of the CMOS world
Universidade Federal do Rio Grande do Sul –
As technology scaling reaches the physical limits of silicon,
several new problems must be addressed, from the design of
low-power but high performance circuits, to the reliability issue
of weak transistors and mixed technologies (nanowrires, SET, etc).
These technological problems will impact several layers of the
current abstraction stack that covers computers and software
production. New architectural solutions that explore parallelism
at different granularity must be sought, not only for
performance/energy trade-offs, but also as a means to assure
reliability, fault tolerance and yield, thanks to regularity. This
talk presents some ideas on this direction, covering future
processor architectures and quaternary logic circuits, discussing
technologies that can deal with this multivariable problem.
Luigi Carro was born in Porto Alegre, Brazil,
in 1962. He received the Electrical Engineering and the MSc
degrees from Universidade Federal do Rio Grande do Sul (UFRGS),
Brazil, in 1985 and 1989, respectively. From 1989 to 1991 he
worked at ST-Microelectronics, Agrate, Italy, in the R&D group. In
1996 he received the Dr. degree in the area of Computer Science
from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. He
is presently a professor at the Applied Informatics Department at
the Informatics Institute of UFRGS, in charge of Computer
Architecture and Organization disciplines at the undergraduate
levels. He is also a member of the Graduation Program in Computer
Science at UFRGS, where he is co-responsible for courses on
Embedded Systems, Digital signal Processing, and VLSI Design. His
primary research interests include embedded systems design,
validation, automation and test, fault tolerance for future
technologies and rapid system prototyping. He has published more
than 150 technical papers on those topics and is the author of the
book Digital systems Design and Prototyping (2001-in portuguese)
and co-author of Fault-Tolerance Techniques for SRAM-based FPGAs
(2006-Springer). For the latest news, please check
Seminar organized by the
Date: 2008-Oct-16 Time: 11:00:00 Room: 336
For more information:
Workshop “Metabolism and mathematical models: Two for a tango” – 2nd Edition
Title: Workshop Metabolism and mathematical models: Two for a tango – 2nd Edition
Dates: October 25-26, 2022
Location: This workshop will be held in a virtual way
The topic of this workshop is metabolism in general, with a special focus, although not exclusive, on parasitology. Besides an exploration of the biological, biochemical and biomedical aspects, the workshop will also aim at presenting some of the mathematical modelling, algorithmic theory and software development that have become crucial to explore such aspects.
This workshop is being organised in the context of two projects, both with the Inria European Team Erable. One of the projects involves a partnership with the University of São Paulo (USP), in São Paulo, Brazil, more specifically the Institute of Mathematics and Statistics (IME) and the Institute of Biomedical Sciences – Inria Associated Team Capoeira – and the other involves the Inesc-ID/IST in Portugal, ETH in Zürich and EMBL in Heidelberg – H2020 Twinning Project Olissipo.
The workshop is open to all members of these two projects but also, importantly, to the community in general.
The program and more details are available here.