Pui-In (Elvis) Mak,

University of Macao – Macao, China –

Abstract:

Technology downscaling has led to a continuous reduction of supply voltage (VDD) to maintain device reliability. High-voltage-(HV)-enabled analog/RF circuits have emerged as a feasible alternative to cope with the nanometer technologies at low cost. An elevated VDD directly open up much flexibility in defining circuit topologies while preserving sufficient voltage headroom for signal swing. Evidently, design-for-reliability is essential to avoid overstress on each device.
This lecture starts by introducing the concept of HV-enabled analog/RF circuits. State-of-the-art works are discussed to justify their advantageous features over wide range of aspects. Our recently proposed 2xVDD RF techniques for enhancing circuit performances without leveraging reliability are then presented. A HV-enabled mobile-TV tuner RF front-end is fabricated in 90-nm CMOS 1 as a proof-of-concept prototype. It include a cascode-cascade inverter-based low-noise amplifier, a linearized programmable C-2C attenuator with a reliable overdrive control, a gain roll-off compensation path and dual cascode I/Q mixer drivers. Stress-conscious circuit topologies and gate-drain-source engineering techniques enable reliable 2-V operation with standard 1-V thin-oxide transistors.

 

Date: 2009-Nov-04     Time: 17:00:00     Room: VA2 (Pav. Civil – IST Alameda)

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