Power and Delay Comparison of Binary and Quaternary Arithmetic Circuits
R – INESC-ID Lisboa –
Interconnections play a crucial role in deep sub-micron designs since they dominate the delay, power and area. This is especially critical for modern million-gates FPGAs, where as much as 90% of chip area is devoted to interconnections. Multiple-valued logic allows for the reduction of the required number of signals in the circuit, hence can serve as a means to effectively curtail the impact of interconnections. We present in this paper a comparison of binary and quaternary implementations of arithmetic modules based on lookup table structures using voltage-mode circuits. Our assessment demonstrates that significant power reduction is possible through the use of quaternary structures, with very low delay penalties.
- Date and local
- Tuesday, November, 3 2009, 11h30, room 336 at INESC-ID, Lisbon.
- More info
Seminars page of INESC-ID
Seminar organized by the
ALGOS group (algos.inesc-id.pt)
Date: 2009-Nov-03 Time: 11:30:00 Room: 336
For more information:
- +351 213100399
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