Abstract:

Arithmetic additive test pattern generators (AdTPG) are being proposed recently as an lternative to the linear feedback shift registers (LFSR) thanks to their reduced area overhead impact. Similar to the case of LFSR, the compactness of the information required into memory and the test generation time required to achieve a specified fault coverage level (FC) has a significant impact on resources required and thus to the quality of the test.

In this seminar, a new approach to the test preparation is proposed. It has been observed that two different preparation methodologies that are independent can be combined in order to achieve a better quality test if compared to the results obtained by their separate application. Experiments show that the combined strategy
also improves previously published results.

Prof. Salvador Manich-Bou graduated as an Industrial Engineer in 1992 and obtained his doctor’s degree in Electronic Engineering in 1998 at the Universitat Politécnica de Catalunya (UPC). He is presently an Associate Professor at the Electronic Engineering Department. He is teaching electronic lectures in different engineering branches. He is member of the Microelectronics and Test research group. His research activity is focused in generation strategies of test patterns and techniques for characterization and modeling of the power consumption of ICs. He is also working in low power design for test.

Date: 2005-Mar-18     Time: 15:30:00     Room: Room E8 – North Tower – EEC Department, IST

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