Computer Architecture: an experience on performance and power
Filipa Duarte, PhD,
In this presentation, I will introduce memory copy hardware accelerator (MCHA) and the benefits of its usage in a multiprocessor platform supporting an explicit send and receive programming model. The MCHA redirects the destination address to the original data in the cache through an indexing table tightly coupled with a cache. Therefore, it avoids cache pollution as there is no overwrite of the copied data over original data and vice-versa. Moreover, the MCHA reduces the number of instructions executed when performing a memory copy when compared with the classical software implementation. Thus, as the copy is performed in hardware, it is faster, providing a speedup of 2.97.
In the second part of the presentation, I will introduce a biomedical system developed at IMEC, targeting the ECG application. At the centre of the system is the Coolflux BSP processor, that processes heart beat signals collected from several sensors and sends the reports of the analysis to the radio interface. The system has aggressive power and clock management in order to reduce the power consumption of the system. Moreover, I will also introduce the circuit-level techniques as well the architecture optimizations to reach the expected power consumption.
Date: 2010-Apr-30 Time: 14:00:00 Room: 336
For more information:
INESC-ID ESR Talks – February 2023
If you are a masters/PhD student or a postdoctoral fellow, come and present your work in an informal and friendly environment – and savour some tasty snacks!
Individual talks will be 10-15 minutes plus time for feedback. Enroll on your selected date by emailing pedro.ferreira[at]inesc-id.pt.
Happening on the second Wednesday of every month (4pm-5pm):
- 15 February (Alves Redol, Room 9)
- 15 March (Alves Redol, Room 9)
- 12 April (Alves Redol, Room 9)
- 10 May (Alves Redol, Room 9)
- 14 June (Alves Redol, Room 9)
- 12 July (Alves Redol, Room 9)
We hope to see you there!