Abstract:

The clock frequency of a digital IC is limited by its slowest paths,
designated by speedpaths. Given the extreme complexity involved in
modeling modern IC technologies, often speedpath predictions provided by
timing analysis tools are not correct. Therefore, several practical
techniques have recently been proposed for design debugging, that combine
silicon stepping of improved versions of a circuit with subsequent
correlation between measured and predicted data. Addressing these issues,
in this talk we proposes a set of techniques that enable the designer to
obtain reduced subsets of paths, guaranteed to contain all the speedpaths
of a given circuit or block. Such subsets can be computed either from
timing models, prior to fabrication, or incorporating actual delay
measurements from fabricated instances.

Date: 2010-May-28     Time: 11:00:00     Room: 04

For more information:

• seminars@algos.inesc-id.pt