Prof. S. Nandy,

Indian Institute of Science


Emerging embedded applications are based on evolving standards (ex. MPEG2/4, H.264/265, IEEE802.11a/b/g/n). Since most of these applications run on handheld devices, there is an increasing need for a single chip solution that can dynamically interoperate between different standards and their derivatives. In order to achieve high resource utilization and low power dissipation, we propose REDEFINE, a Polymorphic ASIC in which specialized hardware units are composed from basic functional units at runtime. It is a ³future-proof² custom hardware solution for multiple applications and their derivatives in a domain.
In this talk, I will provide a broad overview of the architecture of REDEFINE and its hardware aware application synthesis framework. REDEFINE comprises an array of Tiles interconnected in a Honeycomb network. Each Tile comprises a Compute Element and a Router. In the synthesis process, applications described in High Level Language (for ex: C) are compiled into application sub-structures. Each application substructure is hosted onto a set of Compute Elements on REDEFINE to form a Computational Structure that is a functional equivalent of a hardwired unit. In the application synthesis methodology for REDEFINE, application specific Computational Structures are composed and destroyed in both space and time for the different application substructures to support polymorphism in hardware. The characterization, diversity and multiplicity of the functional units in a Compute Element are domain specific. Thus, while the architecture of REDEFINE is application agnostic, the Compute Elements in REDEFINE can be chosen to be domain specific to enable synthesis of hardware accelerators on Reconfigurable Silicon Cores.


Date: 2011-Jul-21     Time: 14:00:00     Room: Sala de reuniões do DEEC

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