Stephan Wong,

Technical University of Delft


In this presentation, we present the rationale and design the Delft reconfigurable and parameterized VLIW processor called rho VEX (rVEX in short). Its architecture is based on the Lx/ST200 ISA developed by HP and STMicroelectronics. We implemented the processor on an FPGA as an open-source softcore and made it freely available. Using the rVEX, we intend bridge the gap between general-purpose and application-specific processing through parametrization of many architectural and organizational features of the processor. The initial set of parameters include: instruction set (number and type of supported instructions), the number and type of functional units (FUs), issue-width (number of slots), register file size, memory bandwidth. The parameters can be set in a static or dynamic manner in order to provide the best performance or the best utilization of available resources on the FPGA. A complete toolchain including a C compiler and a simulator is freely available. Any application written in C can be mapped to the rVEX processor. This VLIW processor is able to exploit the instruction level parallelism (ILP) inherent in an application and make its execution faster compared to a RISC processor system. Recent developments will be presented. The rVEX is currently being further developed within an EU-funded project called ERA: Embedded Reconfigurable Architectures.


Date: 2011-Jul-26     Time: 16:30:00     Room: 336

For more information: