Pedro Trancoso,

University of Cyprus


Processor design has evolved considerably in the last years. In order to cope with Moore s Law, processors became increasingly complex and their power consumption reached unacceptable levels. This led to a paradigm shift to what currently is the de-facto standard the multi-core processors. Even though these processors are able to offer high performance at a lower power consumption level, they introduce new challenges, particularly as the number of cores per processor increases. It is expected that in the future we will have thousands of cores within a chip and that there will be cores of different characteristics on the same chip. Such processors are known as heterogeneous many-core chips. In this presentation an overview of the past, present, and future research projects dealing with these issues will be given. The focus is on two topics: TFlux, an implementation of the Data-Driven Multithreading execution model and the Fine-grain parallelism for different multi-cores and accelerators. In addition, results from different applications and scheduling for the Intel Single-chip Cluster Computer (SCC) 48-core processor willbe presented. All projects are unified under a common umbrella: the vision that future heterogeneous many-core processors will be packaged together with a virtualization layer hiding the complexity and managing the resources to exploit the best performance.


Date: 2012-Dec-20     Time: 14:00:00     Room: 020

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