Future Many-core Processors: Challenges and Solutions
Pedro Trancoso,
University of Cyprus –
Abstract:
Processor design has evolved considerably in the last years. In order to cope with Moore s Law, processors became increasingly complex and their power consumption reached unacceptable levels. This led to a paradigm shift to what currently is the de-facto standard the multi-core processors. Even though these processors are able to offer high performance at a lower power consumption level, they introduce new challenges, particularly as the number of cores per processor increases. It is expected that in the future we will have thousands of cores within a chip and that there will be cores of different characteristics on the same chip. Such processors are known as heterogeneous many-core chips. In this presentation an overview of the past, present, and future research projects dealing with these issues will be given. The focus is on two topics: TFlux, an implementation of the Data-Driven Multithreading execution model and the Fine-grain parallelism for different multi-cores and accelerators. In addition, results from different applications and scheduling for the Intel Single-chip Cluster Computer (SCC) 48-core processor willbe presented. All projects are unified under a common umbrella: the vision that future heterogeneous many-core processors will be packaged together with a virtualization layer hiding the complexity and managing the resources to exploit the best performance.
Date: 2012-Dec-20 Time: 14:00:00 Room: 020
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Upcoming Events
INESC Brussels HUB Winter Meeting 2023

This edition of the HUB Winter Meeting will be co-organised with Science Business and will take place on the 30 and 31 January, in Lisbon, at Instituto Superior Técnico, Department of Computer Science and Engineering.
Please see below a summary of the agenda, this will be updated on the INESC Brussels HUB website regularly (confirmed speakers and other relevant info). Places for onsite participation are limited so registration is mandatory. Online participants will be sent a ZOOM link for each specific session on the 27th January.
INESC Brussels HUB website: https://hub.inesc.pt/
Monday, 30 January
a) Digital Europe Programme & Chips Act: state of play and possibilities for INESC.
9h to 10h30 GMT
(Exclusive for INESC researchers and administrators).
b) Science Business: how can INESC tap into Science Business network, activities and communications tools.
(Exclusive for INESC researchers and administrators).
c) Networking Lunch (for all onsite participants).
d) Roundtable: From rhetoric to reality – Embedding international strategy in the DNA of research organisations.
(Closed-door, roundtable workshop, Chatham House rules, open to INESC researchers and administrators, external participants by invitation only).
e) Networking Dinner
(By invitation only – INESC researchers participating onsite in the event are elegible to join).
Tuesday, 31 January
f) Workshop: How they did it? Strategic positioning for structural success in Horizon Europe: a discussion of best practices.
(Exclusive for INESC researchers, administrators and international invited speakers).
g) The public consultation on European R&I Programmes: Towards FP10.
(Closed-door, roundtable workshop, Chatham House rules, open to INESC researchers and administrators, external participants by invitation only).
h) Networking Lunch (for all onsite participants).
i) Management Committee meeting (Directors and POB members)
The HUB Winter Meeting aims at bringing together researchers and administrators from the 5 INESC institutes, affiliated higher education institutions in Portugal and abroad, with key European and global players, to:
– Discuss key research and innovation issues at EU level.
– Inform institutional policy and strategy.
– Exchange best-practices about R&I management, career development and policy positioning.
– Promote, discuss and deliver vision, visibility, networking and impactful communication.
– Create, identify and deepen partnerships and collaboration opportunities for collaborative R&I.