José Monteiro,

Inesc-ID

Abstract:

Despite the aggravation of issues such as power consumption, noise and
clock skew, caused by increasingly higher clock frequencies, the
synchronous design paradigm continues to be the most widely used in
the project of general VLSI circuits. Under this paradigm, a special
signal, the clock signal, is used to define time-slots to synchronize
the operations among the elements in the circuit. Typically, the
clock signal used for synchronization is a square waveform. It can be
shown that this type of signal is the worst case for power consumption
and induced noise.

In this talk I will argue that global synchronization can be achieved
using a triangular waveform with advantages at many levels. The
smoothness of the waveform (hence, lower frequency components)
translates into significantly lower power consumption and induced
noise when compared with a square clock signal. Additionally, given
its linear variation with time, time references can be defined not
only by the period of the clock signal, but by the varying voltage
level of the triangular waveform. This feature allows for the
reduction of the triangular signal frequency, hence further reducing
the noise and minimizing clock signal degradation. New sequential
elements can be designed to work directly with the triangular
waveform. Alternatively, we propose that triangular waveform can be
used for chip-wide clock distribution, from which a square waveform
can be extracted locally, permitting existing modules to be used
without alterations, thus avoiding any shift from standard design
styles.

 

Date: 2005-Oct-07     Time: 14:00:00     Room: 336


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