Hardware Security: Challenges, Solutions and Opportunities
Chip Hong Chang,
Nanyang Technological University –
The geographical dispersion of chip design activities, coupled with the heavy reliance on third party hardware intellectual properties (IPs), have led to the infiltration of counterfeit and malicious chips into the integrated circuit (IC) design and fabrication flow. Counterfeit chips (such as unauthorized copies, remarked/recycled dice, overproduced and subverted chips or cloned designs) pose a major threat to all stakeholders in the IC supply chain, from designers, manufacturers, system integrators to end users. The consequence they caused to the electronic equipment and critical infrastructure can be disastrous yet identifying compromised ICs is extremely difficult. New attack scenarios could put the integrated electronics ecosystem in dire peril if nothing is done to avert these hardware security treats.
This talk provides an overview of our research effort in hardware security. Constraint-based watermarking and fingerprinting are first introduced as a detection approach to hardware IP copyright protection, which can be augmented by an identity-based signature scheme to enable multiple IP cores marked by different authors in a single chip to be publicly authenticable in the field by the end users. As reusable IPs sold in the form of FPGA configuration bitstreams are vulnerable to cloning, misappropriation, reverse engineering and hardware Trojan (HT) attacks, a pay-per-use liscensing scheme is proposed to assure the secure installation of FPGA IP cores onto contracted devices agreed upon by the IP provider and IP buyer. Side-channel analysis method for HT detection and an active current sensing circuit for fast screening of HT-infected chips will also be presented. The last part of this talk will introduce disorder-based methods to avoid the long-term presence of keys in vulnerable hardware. These methods enable random, unique and physically unclonable device fingerprints to be generated on demand for authentication and other cryptographic applications. The high-quality physical unclonable functions (PUFs) we proposed include the robust RO-PUF for resource-constrained platforms, CMOS image sensor based PUF for sensor-level authentication and the PUFs based on emerging non-volatile memory technologies. Finally, some on-going and future research topics addressing the challenges and opportunities in hardware security will be outlined.
Chip Hong Chang received the B.Eng. (Hons.) degree from the National University of Singapore in 1989, and the M. Eng. and Ph.D. degrees from Nanyang Technological University (NTU) of Singapore, in 1993 and 1998, respectively, and the Postgraduate Diploma for Teaching in Higher Education (PGDipTHE) in 2001 from the National Institute of Education. He served as a Technical Consultant in industry prior to joining the School of Electrical and Electronic Engineering (EEE), NTU, in 1999, where he is currently an Associate Professor. He holds joint appointments with the university as an Assistant Chair of Alumni of the School of Electrical and Electronic Engineering (EEE) from June 2008 to May 2014, the Deputy Director of the Center for High Performance Embedded Systems from February 2000 to December 2011, and the Program Director of the Center for Integrated Circuits and Systems from April 2003 to December 2009. He has coedited two books, published eight book chapters, and more than 200 refereed international journal and conference papers (mostly in IEEE). His current research interests include hardware-oriented security, low power arithmetic circuits, residue number system and digital filter design. He is the co-recipient of the Gold Leaf and Silver Leaf certificates of the 2010 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, and co-author of the finalist of the best paper award in IFIP International Conference on Very Large Scale Integration in 1995 and the finalist of the best student paper competition award for the 2015 IEEE International Symposium on Circuits and Systems to be held in Lisbon, Portugal in May 24, 2015.
Date: 2015-May-27 Time: 11:00:00 Room: Electrical and Computer Engineering Depart. Meeting Room, IST
For more information:
INESC-ID ESR Talks – February 2023
If you are a masters/PhD student or a postdoctoral fellow, come and present your work in an informal and friendly environment – and savour some tasty snacks!
Individual talks will be 10-15 minutes plus time for feedback. Enroll on your selected date by emailing pedro.ferreira[at]inesc-id.pt.
Happening on the second Wednesday of every month (4pm-5pm):
- 15 February (Alves Redol, Room 9)
- 15 March (Alves Redol, Room 9)
- 12 April (Alves Redol, Room 9)
- 10 May (Alves Redol, Room 9)
- 14 June (Alves Redol, Room 9)
- 12 July (Alves Redol, Room 9)
We hope to see you there!