Tiago M Dias,

Instituto Superior de Engenharia de Lisboa (ISEL)


In this talk it will be presented a new, scalable and efficient VLSI architecture for real-time sub-pixel motion estimation. The presented structure is optimized for search strategies using small search ranges, such as hierarchical or sub-pel refinement algorithms. Based on this architecture, a highly modular and configurable motion estimation co-processor will be also presented, capable of estimating optimal motion vectors with any given accuracy and using any known interpolation algorithm. The performance of this processing structure has been evaluated by embedding it in a two-level motion estimation system with minimum memory bandwidth requirements, that estimates half-pixel accurate motion vectors using a two-step search procedure. Experimental results for implementations on ASIC and FPGA devices will be presented, showing that by using this new architecture it is possible to estimate motion vectors up to the 4CIF image format with any given sub-pixel accuracy in real-time.


Date: 2005-Oct-24     Time: 14:00:00     Room: 336

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