Gonçalo Nogueira,

Socionext, Inc –

Abstract:

Size scaling of CMOS transistors has been happening for the past 30 years, with technologies like FinFET or FD-SOI being used recently to make up for limitations found in Bulk technology. With TSMC releasing 5nm FinFET in 2019 (with gate lengths of the order of dozens of atoms wide), design and layout are changing significantly from what is seen in older technologies. This seminar addresses the topic of FinFET from an industry designer’s perspective, with the following content: an introduction to FinFET, design and layout with FinFETs, advantages and challenges, and lastly, the expected future of solid state circuits.

Bio

Gonçalo Nogueira received the B. Sc. Degree in Engineering Sciences and the M. Sc. Degree in Electrical and Computer Engineering from Instituto Superior Técnico (IST), Universidade de Lisboa, in 2013 and 2016, respectively. He worked at INESC-ID with a research grant at the end of 2016 and since August 2017 he has been working in Socionext, Inc. developing high speed data converters with 7nm FinFET technology. His main professional interests are High Speed, R&D, Analog-and-Mixed Signal and State-of-the-Art.

 

Date: 2018-Sep-19     Time: 17:00:00     Room: Room EA4 North Tower, Alameda

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