Ricardo Chaves,

Inesc-ID

Abstract:

This presentation introduces the Trusted Computing problem and proposes a reconfigurable approach to the existing solution, the Trusted Computing module chip.
The new Trusted Computing approach to computation provides additional safety to the user’s data and a higher protection against malicious attacks to the systems. This system is strongly based in encryption algorithms.
Results for a memory based implemented of the AES algorithm in a prototyping XC2VP20 FPGA are also presented. These results suggest speedups up to 751 times for a hybrid implementations of the AES algorithm with only 10% utilization of the reconfigurable device.
Two AES encryption/decryption standalone cores have also been designed and implemented on a prototyping XC2VP20-7 FPGA. Comparisons to state-of-the-art AES cores indicate that the proposed unfolded core outperforms the most recent works by 34% in throughput and requires 68% less reconfigurable area. Experimental results of both folded and unfolded AES cores suggest over 560% improvement in the Throughput/Slice metric when compared to the recent AES related art.

 

Date: 2005-Nov-21     Time: 14:00:00     Room: 336


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