Compiler-Directed Caching in FPGAs using RAM Blocks
University of Southern California –
Configurable architectures, such as Field-Programmable-Gate-Arrays (FPGAs) offer the promise of substantial performance improvements over conventional processors by allowing the implementation of application-specific datapaths that exploit instruction-level parallelism or domain-specific numeric formats and operations. Unfortunately FPGAs are still difficult to program making them inaccessible to the average developer. The standard practice requires developers to express the application program in a hardware-oriented language such as Verilog or VHDL, and synthesize the hardware design using a variety of synthesis tools. This process is awkward and very error-prone making the use of high-level compilation and synthesis tools very desirable.
In this presentation we focus on the utilization of configurable storage structures found in today’s high-end FPGAs, namely discrete registers and RAM blocks to eliminate the external memory accesses of a given hardware implementation. We describe the utilization of a specific compiler transformation – scalar replacement for array variables – and an allocation algorithm that leverages the utilization of RAM blocks in the presence of a limited number of hardware registers. This algorithm, based on a compiler data reuse analysis, determines which data should be cached in the internal RAM blocks and when. The preliminary results, for a set of image/signal processing kernels targeting a Xilinx VirtexTM FPGA device, reveal that despite the increase latency of accessing data in RAM blocks, designs that use them require smaller configurable resources than designs that exclusively use registers, while attaining comparable and in some cases even better performance.
Date: 2006-Jan-03 Time: 15:00:00 Room: 336
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Workshop “Metabolism and mathematical models: Two for a tango” – 2nd Edition
Title: Workshop Metabolism and mathematical models: Two for a tango – 2nd Edition
Dates: October 25-26, 2022
Location: This workshop will be held in a virtual way
The topic of this workshop is metabolism in general, with a special focus, although not exclusive, on parasitology. Besides an exploration of the biological, biochemical and biomedical aspects, the workshop will also aim at presenting some of the mathematical modelling, algorithmic theory and software development that have become crucial to explore such aspects.
This workshop is being organised in the context of two projects, both with the Inria European Team Erable. One of the projects involves a partnership with the University of São Paulo (USP), in São Paulo, Brazil, more specifically the Institute of Mathematics and Statistics (IME) and the Institute of Biomedical Sciences – Inria Associated Team Capoeira – and the other involves the Inesc-ID/IST in Portugal, ETH in Zürich and EMBL in Heidelberg – H2020 Twinning Project Olissipo.
The workshop is open to all members of these two projects but also, importantly, to the community in general.
The program and more details are available here.