Compiler-Directed Caching in FPGAs using RAM Blocks
University of Southern California –
Configurable architectures, such as Field-Programmable-Gate-Arrays (FPGAs) offer the promise of substantial performance improvements over conventional processors by allowing the implementation of application-specific datapaths that exploit instruction-level parallelism or domain-specific numeric formats and operations. Unfortunately FPGAs are still difficult to program making them inaccessible to the average developer. The standard practice requires developers to express the application program in a hardware-oriented language such as Verilog or VHDL, and synthesize the hardware design using a variety of synthesis tools. This process is awkward and very error-prone making the use of high-level compilation and synthesis tools very desirable.
In this presentation we focus on the utilization of configurable storage structures found in today’s high-end FPGAs, namely discrete registers and RAM blocks to eliminate the external memory accesses of a given hardware implementation. We describe the utilization of a specific compiler transformation – scalar replacement for array variables – and an allocation algorithm that leverages the utilization of RAM blocks in the presence of a limited number of hardware registers. This algorithm, based on a compiler data reuse analysis, determines which data should be cached in the internal RAM blocks and when. The preliminary results, for a set of image/signal processing kernels targeting a Xilinx VirtexTM FPGA device, reveal that despite the increase latency of accessing data in RAM blocks, designs that use them require smaller configurable resources than designs that exclusively use registers, while attaining comparable and in some cases even better performance.
Date: 2006-Jan-03 Time: 15:00:00 Room: 336
For more information:
INESC-ID ESR Talks – February 2023
If you are a masters/PhD student or a postdoctoral fellow, come and present your work in an informal and friendly environment – and savour some tasty snacks!
Individual talks will be 10-15 minutes plus time for feedback. Enroll on your selected date by emailing pedro.ferreira[at]inesc-id.pt.
Happening on the second Wednesday of every month (4pm-5pm):
- 15 February (Alves Redol, Room 9)
- 15 March (Alves Redol, Room 9)
- 12 April (Alves Redol, Room 9)
- 10 May (Alves Redol, Room 9)
- 14 June (Alves Redol, Room 9)
- 12 July (Alves Redol, Room 9)
We hope to see you there!