@mastersThesis{LuisRafaeldaGracaAzinheira_9_2019,
   author = "Luis Rafael da Gra{\c c}a Azinheira",
   title = "Deep Architecture for the Versat Reconfigurable Processor (Verilog)",
   year = 2019,
   month = sep,
   type = "Master's Thesis",
   BibTexOrigem = "14570 www.Inesc-ID.pt 2021-08-05"
}

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