Design of a Reconfigurable Many-Core Architecture for High Performance Computing (DreaMachine)

Type: National Project

Duration: from 2012 Feb 01 to 2015 Jan 31

Financed by: FCT

Prime Contractor: INESC-ID (Other)

Development and prototyping of an adaptable/reconfigurable many-core architecture using reconfigurable processors and an adaptable on-chip interconnection network (OCIN) for high performance computing (HPC). Develop a methodology to explore the design space of the architecture. A framework will integrate tools for architecture specification and configuration, for hardware synthesis, for kernel mapping and for architecture simulation.


  • INESC-ID (Other)

Principal Investigators