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- Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units
Mário Pereira Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
ACM Transactions on Reconfigurable Technology and Systems
2022 - On-Board Processing of Synthetic-Aperture Radar Backprojection Algorithm in FPGA
David Mota, Helena Alexandra Sabala Ruivo da Cruz, Mário Pereira Véstias, Pedro José Runa Miranda, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing
2022 - IOb-Cache: A High-Performance Configurable Open-Source Cache
Mário Pereira Véstias, João Vieira Rodrigues de Almeida Roque, João Dias Lopes, José T. de Sousa
Algorithms n. 14, DOI https://doi.org/10.3390/a14080218
2021 - Configurable Hardware Core for IoT Object Detection
Pedro José Runa Miranda, Daniel Garigali Pestana, João Dias Lopes, Rui Policarpo Duarte, Mário Pereira Véstias, Horácio C. Neto, José T. de Sousa
Future Internet vol. 13, n. 11, DOI 10.3390/fi13110280
2021 - A Full Featured Configurable Accelerator for Object Detection with YOLO
Daniel Pestana, Pedro Miranda, João Dias Lopes, Rui Policarpo Duarte, Mário Pereira Véstias, Horácio C. Neto, José T. de Sousa
IEEE Access DOI 10.1109/ACCESS.2021.3081818
2021 - Coarse-Grained Reconfigurable Computing with the Versat Architecture
João Dias Lopes, Mário Pereira Véstias, Rui Policarpo Duarte, Horácio C. Neto, José T. de Sousa
Electronics vol. 10, n. 6, DOI https://doi.org/10.3390/electronics10060669
2021 - A fast and scalable architecture to run convolutional neural networks in low density FPGAs
Mário Pereira Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
Microprocessors and Microsystems vol. 77, n. 103136, DOI 10.1016/j.micpro.2020.103136
2020 - A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs
Mário Pereira Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
IEEE Access vol. 8, DOI 10.1109/ACCESS.2020.3000444
2020 - Moving Deep Learning to the Edge
Mário Pereira Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
Algorithms vol. 13, n. 125, DOI 10.3390/a13050125
2020 - Fast Convolutional Neural Networks in Low Density FPGAs Using Zero-Skipping and Weight Pruning
Mário Pereira Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
Electronics vol. 8, DOI 10.3390/electronics8111321
2019 - A 1.7-mW -92-dBm Sensitivity Low-IF Receiver in 0.13-μm CMOS for Bluetooth LE Applications
Marco Pereira, José T. de Sousa, João Costa Freire, João Caldinhas Vaz
IEEE Transactions on Microwave Theory and Techniques PP(99):1-15
2018
- Hardware Accelerated Backprojection Algorithm on Xilinx UltraScale+ SoC-FPGA for On-Board SAR Image Formation
Rui Policarpo Duarte, Helena Alexandra Sabala Ruivo da Cruz, Mário Pereira Véstias, José T. de Sousa, Horácio C. Neto
2023 European Data Handling & Data Processing Conference (EDHPC), IEEE, - Optimization of a Synthetic-Aperture Radar Image Processing Algorithm for SoC-FPGAs
Helena Alexandra Sabala Ruivo da Cruz, Mário Pereira Véstias, José Monteiro, Horácio C. Neto, José T. de Sousa, Rui Policarpo Duarte
REC2022 - XVIII Jornadas sobre Sistemas Reconfiguráveis, - Power Efficiency and Performance for Embedded and HPC Systems with Custom CGRAs
Nuno Paulino, João C. Ferreira, João Cardoso, João Dias Lopes, Mário Pereira Véstias, José T. de Sousa
Design Automation and Test in Europe Conference,
2020 - Implementing CNNs using a Linear Array of Full Mesh CGRAs
Valter Mário, João Dias Lopes, Mário Pereira Véstias, José T. de Sousa
Applied Reconfigurable Computing,
2020 - Redes Neuronais Convolucionais em FPGA de Baixa Densidade
Mário Pereira Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
XVI Jornadas Sobre Sistemas Reconfiguráveis (REC 2020), Instituto Superior Técnico, Lisboa - Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA
Mário Pereira Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
Field-Programmable Logic and Applications (FPL), IEEE, IEEE,
2019 - Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores
Luís Fiolhais, Fernando Manuel Duarte Gonçalves, Rui Policarpo Duarte, Mário Pereira Véstias, José T. de Sousa
IEEE International Symposium on Circuits and Systems,
2019 - Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs
Mário Pereira Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
International Conference on Field Programmable Logic and Applications (FPL), IEEE, IEEE,
2018 - Implementação Eficiente de Múltiplos Produtos Internos com DSP
Mário Pereira Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
Jornadas sobre SIstemas Reconfiguráveis,
2018
- Modular system for real-time on-board processing of synthetic aperture radar images
Rui Policarpo Duarte, Mário Pereira Véstias, José T. de Sousa
2022