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- Investigation on new reconfigurable architectures and execution models to leverage the information gathered, at compile time, using a predefined SRL specification. - Identification of balancing mechanisms to apply in the granularity of the resource adaptation to mitigate and/or hide the impact of the reconfiguration process. - Integration of data-streaming mechanisms to generate the memory access patterns extracted by the SRL. - Evaluation of the resulting processing structure using a comprehensive set of benchmark applications based on either a state-of-the-art FPGA device or using the FPGA infrastructure available at Amazon EC2. - Report the achieved results in the form of a research article.