Research grant in project SARRROCA, “Synthetic Aperture Radar Robust Reconfigurable Optimized Computing Architecture” - ref: PTDC/EEI-HAC/31819/2017Bolsa de investigação no projeto SARRROCA, “Synthetic Aperture Radar Robust Reconfigurable Optimized Computing Architecture” - ref: PTDC/EEI-HAC/31819/2017
Type of Position: Research Fellowship (Bolsa de Investigação)
Type of Contract: Research grant
Duration: 6 Months
Closed at: 2019-Sep-28
One research grant(s) Bolsa de Investigacão - Mestre is now available in project SARRROCA, “Synthetic Aperture Radar Robust Reconfigurable Optimized Computing Architecture” - ref: PTDC/EEI-HAC/31819/2017 funded by FCT/MCTES through national funds, and, where appropriate, POCI - Programa Operacional Competitividade e Internacionalização e PORLisboa – Programa Operacional Regional de Lisboa, under the following conditions:
Duration Six months from 1 of October 2019. The grant may be renewed within the period of the project, not exceeding the maximum period set by FCT for such grants. Renewal is subject to suitable performance
Legislation A fellowship contract will be celebrated according to the Regulations for Research Grants of the Foundation for Science and Technology in force the INESC ID Grant regulations approved by FCT, and to the Status of Scientific Research Fellow (Lei nº 40/2004 de 18 de Agosto, and its successive amendments).
Monthly amount The monthly amount of the grant 989,70€ is in accordance with the values stipulated in the “Regulations for Research Grants of the Foundation for Science and Technology” in force (https://www.fct.pt/apoios/bolsas/regulamentos.phtml.pt) and (http://www.fct.pt/apoios/bolsas/valores) and INESC-ID Lisboa Grant Regulations approved by FCT, and shall be rendered through a monthly bank transfer to an account held by the grantee
Objectives / summary This research work aims to develop a fault-tolerant embedded system using Xilinx FPGAs. The research work will involve designing novel hardware architectures and study and implementation of adequate fault-tolerant mechanisms. Expected outputs of this work are the implementation of prototypes for real-time fault-tolerant architectures.
Required education Level and research experience The candidate should have an MSc degree in Computer Science and Engineering, or Electrical and Electronic Engineering and research project experience in System on a Chip design using FPGAs from Xilinx. The candidate should be familiarized with most common fault-tolerance mechanisms on FPGAs. Language skills - proficiency in English. Preference will be given to candidates willing to pursue a PhD degree.
Rui António Policarpo Duarte