Compilation Abstraction and Hardware Adaptation for Specialized and General-Purpose Computing Unification (UNIFY)

Type: National Project Project

Duration: from 2023 Mar 10 to 2026 Mar 09

Financed by: FCT

Prime Contractor: INESC (Other)

Project Web Site:

The ever-increasing amount of data availability and the consequent algorithmic advances have increased the awareness about the performance and efficiency limitations of current General-Purpose Processors (GPPs). As a result, a gradual stagnation has been observed in the development of new GPP architectures, opening the space for the exploration of architectural specialization as an economically viable solution to cope with the current challenges for energy-efficient computing.  
This new specialization trend has shifted the computing paradigm to a new class of Domain-Specific Architectures (DSAs). These accelerators often rely on unconventional mechanisms/techniques that are usually deemed unfit for GPPs, such as data streaming and reconfigurable technologies. This simultaneous adoption of new compiler technologies and new architecture innovations has been recognized as the most prominent alternative to avoid the foreseeable fragmentation between specialized and general-purpose computing.
Accordingly, the main objective of UNIFY project is to tackle this ambitious challenge, by recognizing that the starting steps towards a unification of these paradigms lie in extending compilation tools to abstract the application structural information from the characteristics of the underlying hardware.
To tackle this objective, a new Structural Representation Language (SRL) specification shall be proposed to allow the automatic detection and representation of deterministic and non-deterministic computing structures and memory access schemes. The development of the envisaged SRL will be complemented with the deployment of an open-source framework comprising new compiler extensions to infer SRL constructs from the compiler's internal representation language. Such constructs will be then translated back either to general-purpose machine-code, accelerator code, or for mapping to DSL constructs (targeting DSAs). Such a new SRL (and corresponding compilation framework) will exploit the information gathered during compilation to support the definition and adaptation of the underlying reconfigurable processing architectures supported by data streaming schemes (deployed either as functional units within a general-purpose pipeline or as co-accelerators within a heterogeneous computing platform), thus promoting runtime domain-specific specialization, resource management, and performance and energy consumption balancing.

Principal Investigators