The INESC-ID Distinguished Lectures are back. For the first edition of this renewed series, INESC-ID will welcome Professor Mark Horowitz from Stanford University for a talk titled “Life Post Moore’s Law: The New Design Frontier”.

Date & Time: 23 March, 14h30

Location: Room FA2 at Instituto Superior Técnico

Abstract: For over 50 years, information technology has relied upon Moore’s Law: providing, for the same cost, 2x the number of logic transistors that were possible a few years prior.  For much of that time, the smaller devices also provided dramatic energy and performance improvement through Dennard Scaling, but that scaling ended over a decade ago.  While technology scaling continues, per transistor cost is no longer scaling in the advanced nodes. In this post Moore’s Law reality, further price/performance improvement follows only from improving the efficiency of applications using innovative hardware and software techniques.

Unfortunately, this need for innovative system solutions runs smack into the enormous complexity of designing and debugging contemporary VLSI based hardware/software platforms; a task so large it has caused the industry to consolidate, moving it away from innovation. The result is a set of platforms aim at different computing markets. To overcome this challenge, we need to develop a new design approach and tools to enable small groups of application experts to selectively extend the performance of those successful platforms.

Like the ASIC revolution in the 1980s, the goal of this approach is to enable a new set of designers, then board level logic designers, now application experts, to leverage the power of customized silicon solutions.  Like then, these tools won’t initially be useful for current chip designers, but over time will underly all designs.  In the 1980s to provide access to logic designers, the key technologies were logic synthesis, simulation, and placement/routing of their designs to gate arrays and std cells.  Today, the key is to realize you are creating an “app” for an existing platform, and not creating the system solution from scratch (which is both too expensive and error prone), and to leverage the fact that modern “chips” are made of many chiplets.  The new approach must provide a design window familiar to application developers, with similar descriptive, performance tuning, and debug capabilities. These new tools will be tied to highly capable platforms that are used as the foundation, like the appStore model for mobile phones. This talk will try to convince you this might be possible, and where innovative design/tools are needed.

Bio:  “Professor Horowitz initially focused on designing high-performance digital systems by combining work in computer-aided design tools, circuit design, and system architecture. During this time, he built a number of early RISC microprocessors, and contributed to the design of early distributed shared memory multiprocessors. In 1990, Dr. Horowitz took leave from Stanford to help start Rambus Inc., a company designing high-bandwidth memory interface technology. After returning in 1991, his research group pioneered many innovations in high-speed link design, and many of today’s high speed link designs are designed by his former students or colleagues from Rambus.

In the 2000s he started a long collaboration with Prof. Levoy on computational photography, which included work that led to the Lytro camera, whose photographs could be refocused after they were captured.. Dr. Horowitz’s current research interests are quite broad and span using EE and CS analysis methods to problems in neuro and molecular biology to creating new agile design methodologies for analog and digital VLSI circuits. He remains interested in learning new things, and building interdisciplinary teams.” – from the Stanford University webpage.